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DATA SHEET
MOS INTEGRATED CIRCUIT
PD442012L-X
2M-BIT CMOS STATIC RAM 128K-WORD BY 16-BIT EXTENDED TEMPERATURE OPERATION
Description
The PD442012L-X is a high speed, low power, 2,097,152 bits (131,072 words by 16 bits) CMOS static RAM. The PD442012L-X has two chip enable pins (/CE1, CE2) to extend the capacity. The PD442012L-X is packed in 48-pin plastic TSOP (I).
Features
* 131,072 words by 16 bits organization * Fast access time: 70, 85, 100, 120, 150, 200 ns (MAX.) * Byte data control: /LB (I/O1 - I/O8), /UB (I/O9 - I/O16) * Low voltage operation (B version: VCC = 2.7 to 3.6 V, C version: VCC = 2.2 to 3.6 V, D version: VCC = 1.8 to 3.6 V)
5
* Low VCC data retention (B version: 2.0 V (MIN.), C version: 1.5 V (MIN.), D version: 1.5 V (MIN.)) * Operating ambient temperature: TA = -25 to +85 C * Output Enable input for easy application * Two Chip Enable inputs: /CE1, CE2
Part number Access time ns (MAX.) Operating supply voltage V 2.7 to 3.6 2.2 to 3.6 1.8 to 3.6 Operating ambient temperature C -25 to +85 At operating mA (MAX.) 35 Supply current At standby A (MAX.) 4 At data retention A (MAX.) 4
PD442012L-BxxX PD442012L-CxxX PD442012L-DxxX
Note
70, 85 100, 120 150, 200
Note Under development
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.
Document No. M14274EJ3V0DS00 (3rd edition) Date Published November 1999 NS CP (K) Printed in Japan
The mark 5 shows major revised points.
(c)
1999
PD442012L-X
Ordering Information
Part number Package Access time ns (MAX.) 70 Operating supply voltage V 2.7 to 3.6 Operating temperature C -25 to +85 Remark
PD442012LGY-B70X-MJH PD442012LGY-B70X-MKH PD442012LGY-B85X-MJH PD442012LGY-B85X-MKH PD442012LGY-C10X-MJH PD442012LGY-C10X-MKH PD442012LGY-C12X-MJH PD442012LGY-C12X-MKH PD442012LGY-D15X-MJH Note PD442012LGY-D15X-MKH Note PD442012LGY-D20X-MJH Note PD442012LGY-D20X-MKH Note
48-pin Plastic TSOP (I) (12x18) (Normal bent) 48-pin Plastic TSOP (I) (12x18) (Reverse bent) 48-pin Plastic TSOP (I) (12x18) (Normal bent) 48-pin Plastic TSOP (I) (12x18) (Reverse bent) 48-pin Plastic TSOP (I) (12x18) (Normal bent) 48-pin Plastic TSOP (I) (12x18) (Reverse bent) 48-pin Plastic TSOP (I) (12x18) (Normal bent) 48-pin Plastic TSOP (I) (12x18) (Reverse bent) 48-pin Plastic TSOP (I) (12x18) (Normal bent) 48-pin Plastic TSOP (I) (12x18) (Reverse bent) 48-pin Plastic TSOP (I) (12x18) (Normal bent) 48-pin Plastic TSOP (I) (12x18) (Reverse bent)
B version
85
100
2.2 to 3.6
C version
120
150
1.8 to 3.6
D version
200
Note Under development
2
Data Sheet M14274EJ3V0DS00
PD442012L-X
Pin Configurations (Marking Side)
/xxx indicates active low signal. 48-pin Plastic TSOP (I) (12x18) (Normal bent) x [ PD442012LGY-BxxX-MJH ] [ PD442012LGY-CxxX-MJH ] [ PD442012LGY-DxxX-MJH ]
5
A15 A14 A13 A12 A11 A10 A9 A8 NC NC /WE CE2 IC /UB /LB NC NC A7 A6 A5 A4 A3 A2 A1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
A16 NC GND I/O16 I/O8 I/O15 I/O7 I/O14 I/O6 I/O13 I/O5 VCC I/O12 I/O4 I/O11 I/O3 I/O10 I/O2 I/O9 I/O1 /OE GND /CE1 A0
A0 - A16 /CE1, CE2 /WE /OE /LB, /UB VCC GND NC IC
Note
: Address inputs : Chip Enable 1, 2 : Write Enable : Output Enable : Byte data select : Power supply : Ground : No Connection : Internal Connection
I/O1 - I/O16 : Data inputs / outputs
Note Leave this pin unconnected or connect to GND. Remark Refer to Package Drawings for the 1-pin marking.
Data Sheet M14274EJ3V0DS00
3
PD442012L-X
48-pin Plastic TSOP (I) (12x18) (Reverse bent) x [ PD442012LGY-BxxX-MKH ] [ PD442012LGY-CxxX-MKH ] [ PD442012LGY-DxxX-MKH ]
5
A16 NC GND I/O16 I/O8 I/O15 I/O7 I/O14 I/O6 I/O13 I/O5 VCC I/O12 I/O4 I/O11 I/O3 I/O10 I/O2 I/O9 I/O1 /OE GND /CE1 A0
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
A15 A14 A13 A12 A11 A10 A9 A8 NC NC /WE CE2 IC /UB /LB NC NC A7 A6 A5 A4 A3 A2 A1
A0 - A16 /CE1, CE2 /WE /OE /LB, /UB VCC GND NC IC
Note
: Address inputs : Chip Enable 1, 2 : Write Enable : Output Enable : Byte data select : Power supply : Ground : No Connection : Internal Connection
I/O1 - I/O16 : Data inputs / outputs
Note Leave this pin unconnected or connect to GND. Remark Refer to Package Drawings for the 1-pin marking.
4
Data Sheet M14274EJ3V0DS00
PD442012L-X
Block Diagram
VCC GND A0 A16
Address buffer
Row decoder
Memory cell array 2,097,152 bits
I/O1 - I/O8 I/O9 - I/O16 Input data controller
Sense / Switch Column decoder
Output data controller
Address buffer
/CE1 CE2
/LB /UB /WE
/OE
Data Sheet M14274EJ3V0DS00
5
PD442012L-X
Truth Table
/CE1 CE2 /OE /WE /LB /UB Mode I/O1 - I/O8 H x L x L H x x H L x x H H x x x L L H x L L L H x x x x H x x x L H L L H L H Output disable Word read Lower byte read Upper byte read Word write Lower byte write Upper byte write Not selected High impedance DOUT DOUT High impedance DIN DIN High impedance High impedance High impedance DOUT High impedance DOUT DIN High impedance DIN High impedance ISBNote ICCA Not selected High impedance I/O I/O9 - I/O16 High impedance ISB Supply current
Note /CE1, CE2 = VIH or VIL Remark x : Don't care
6
Data Sheet M14274EJ3V0DS00
PD442012L-X
Electrical Specifications
Absolute Maximum Ratings
Parameter Supply voltage Input / Output voltage Operating ambient temperature Storage temperature Symbol VCC VT TA Tstg Condition Rating -0.5
Note
Unit V V C C
to +4.0
-0.5 Note to VCC+0.4 (4.0 V MAX.) -25 to +85 -55 to +125
Note -3.0 V (MIN.) (Pulse width : 30 ns)
Caution Exposing the device to stress above those listed in Absolute Maximum Rating could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Recommended Operating Conditions
Parameter Symbol Condition
PD442012L-BxxX PD442012L-CxxX PD442012L-DxxX
MIN. MAX. 3.6 VCC+0.4 - -
Note
Unit
MIN. 2.2 2.4 2.0 - -0.3
Note
MAX. 3.6 VCC+0.4 VCC+0.3 - +0.3 +85
MIN. 1.8 2.4 2.0 1.6 -0.3
Note
MAX. 3.6 VCC+0.4 VCC+0.3 VCC+0.2 +0.2 +85 V C V V
Supply voltage High level input voltage
VCC VIH 2.7 V VCC 3.6 V 2.2 V VCC < 2.7 V 1.8 V VCC < 2.2 V
2.7 2.4 - - -0.3
Low level input voltage Operating ambient temperature
VIL TA
+0.5 +85
-25
-25
-25
Note -1.5 V (MIN.) (Pulse width: 30 ns)
Capacitance (TA = 25 C, f = 1 MHz)
Parameter Input capacitance Input / Output capacitance Symbol CIN CI/O VIN = 0 V VI/O = 0 V Test condition MIN. TYP. MAX. 8 10 Unit pF pF
Remarks 1. VIN : Input voltage VI/O : Input / Output voltage 2. These parameters are periodically sampled and not 100% tested.
Data Sheet M14274EJ3V0DS00
7
PD442012L-X
DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
Parameter Symbol Test condition VCC 2.7 V VCC 2.2 V VCC 1.8 V Unit
PD442012L-BxxX PD442012L-CxxX PD442012L-DxxX
MIN. TYP. MAX. MIN. TYP. MAX. MIN. TYP. MAX. Input leakage current I/O leakage current Operating supply current ICCA1 ILO VI/O = 0 V to VCC, /CE1 = VIH or CE2 = VIL or /WE = VIL or /OE = VIH /CE1 = VIL, CE2 = VIH, Minimum cycle time, II/O = 0 mA ICCA2 /CE1 = VIL, CE2 = VIH, II/O = 0 mA VCC 2.7 V VCC 2.2 V ICCA3 /CE1 0.2 V, CE2 VCC - 0.2 V, Cycle = 1 MHz, II/O = 0 mA, VIL 0.2 V, VIH VCC - 0.2 V Standby supply current ISB VCC 2.7 V VCC 2.2 V - - - - - 0.3 VCC 2.7 V VCC 2.2 V ISB2 CE2 0.2 V VCC 2.7 V VCC 2.2 V ISB3 /LB = /UB VCC - 0.2 V, /CE1 0.2 V, CE2 VCC - 0.2 V High level output voltage VOH IOH = -0.5 mA VCC 2.7 V VCC 2.2 V Low level output voltage VOL IOL = 1.0 mA VCC 2.7 V VCC 2.2 V 2.4 - - 0.4 - - 0.3 - - 0.3 - - - - 0.6 - - 4 - - 4 - - 4 - - 2.4 1.8 - 0.4 - - - - - 0.3 0.25 - 0.3 0.25 - 0.3 0.25 - 6 - 0.6 0.6 - 4 3.5 - 4 3.5 - 4 3.5 - 2.4 1.8 1.5 0.4 V - - - - - 0.3 0.25 0.2 0.3 0.25 0.2 0.3 0.25 0.2 6 5 0.6 0.6 0.6 4 3.5 3 4 3.5 3 4 3.5 3 V mA VCC 2.7 V VCC 2.2 V - - - - - - - 35 - - 10 - - 8 - - - - - - - 35 20 - 10 8 - 8 - - - - - - - 35 20 15 10 8 6 8 mA -1.0 +1.0 -1.0 +1.0 -1.0 +1.0 ILI VIN = 0 V to VCC -1.0 +1.0 -1.0 +1.0 -1.0 +1.0
A
A
/CE1 = VIH or CE2 = VIL or /LB = /UB = VIH, /CE1, CE2 = VIH or VIL VCC 2.7 V VCC 2.2 V
ISB1
/CE1 VCC - 0.2 V, CE2 VCC - 0.2 V
A
Remarks 1. VIN : Input voltage VI/O : Input / Output voltage 2. These DC characteristics are in common regardless of package types and access time.
8
Data Sheet M14274EJ3V0DS00
PD442012L-X
AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
AC Test Conditions [ PD442012L-B70X, PD442012L-B85X ] Input Waveform (Rise and Fall Time 5 ns)
2.4 V 1.5 V 0.5 V Test points 1.5 V
Output Waveform
1.5 V
Test points
1.5 V
Output Load 1TTL + 50 pF [ PD442012L-C10X, PD442012L-C12X ] Input Waveform (Rise and Fall Time 5 ns)
2.0 V 1.1 V 0.3 V Test points 1.1 V
Output Waveform
1.1 V
Test points
1.1 V
Output Load 1TTL + 30 pF [ PD442012L-D15X, PD442012L-D20X ] Input Waveform (Rise and Fall Time 5 ns)
1.6 V 0.9 V 0.2 V Test points 0.9 V
Output Waveform
0.9 V
Test Points
0.9 V
Output Load 1TTL + 30 pF
Data Sheet M14274EJ3V0DS00
9
PD442012L-X
Read Cycle
Parameter
Symbol
VCC 2.7 V
VCC 2.2 V
VCC 1.8 V
Unit
Condition
PD442012L PD442012L PD442012L PD442012L PD442012L PD442012L
-B70X -B85X -C10X -C12X -D15X -D20X
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. Read cycle time Address access time /CE1 access time CE2 access time /OE to output valid /LB, /UB to output valid Output hold from address change /CE1 to output in low impedance CE2 to output in low impedance /OE to output in low impedance /LB, /UB to output in low impedance /CE1 to output in high impedance CE2 to output in high impedance /OE to output in high impedance /LB, /UB to output in high impedance tRC tAA tCO1 tCO2 tOE tBA tOH 10 70 70 70 70 35 70 10 85 85 85 85 40 85 10 100 100 100 100 50 100 10 120 120 120 120 60 120 10 150 150 150 150 70 150 10 200 200 200 200 100 200 ns ns ns ns ns ns ns Note 1
tLZ1
10
10
10
10
10
10
ns
Note 2
tLZ2
10
10
10
10
10
10
ns
tOLZ
5
5
5
5
5
5
ns
tBLZ
10
10
10
10
10
10
ns
tHZ1
25
30
35
40
50
70
ns
tHZ2
25
30
35
40
50
70
ns
tOHZ
25
30
35
40
50
70
ns
tBHZ
25
30
35
40
50
70
ns
Notes 1. The output load is 1TTL + 50 pF (PD442012L-BxxX) or 1TTL + 30 pF (PD442012L-CxxX, -DxxX). 2. The output load is 1TTL + 5 pF. Remark These AC characteristics are in common regardless of package types.
10
Data Sheet M14274EJ3V0DS00
PD442012L-X
Read Cycle Timing Chart
tRC
Address (Input) tAA /CE1 (Input) tCO1 tLZ1 tHZ1 tOH
CE2 (Input)
tCO2 tLZ2 tHZ2
/OE (Input) tOE tOLZ /LB, /UB (Input) tBA tBLZ I/O (Output) High impedance Data out tBHZ tOHZ
Remark
In read cycle, /WE should be fixed to high level.
Data Sheet M14274EJ3V0DS00
11
PD442012L-X
Write Cycle
Parameter
Symbol
VCC 2.7 V
VCC 2.2 V
VCC 1.8 V
Unit
Condition
PD442012L PD442012L PD442012L PD442012L PD442012L PD442012L
-B70X -B85X -C10X -C12X -D15X -D20X
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. Write cycle time /CE1 to end of write CE2 to end of write /LB, /UB to end of write Address valid to end of write Address setup time Write pulse width Write recovery time Data valid to end of write Data hold time /WE to output in high impedance Output active from end of write tWC tCW1 tCW2 tBW tAW tAS tWP tWR tDW tDH tWHZ 70 55 55 55 55 0 50 0 30 0 25 85 70 70 70 70 0 55 0 35 0 30 100 80 80 80 80 0 60 0 40 0 35 120 100 100 100 100 0 85 0 60 0 40 150 120 120 120 120 0 100 0 80 0 50 200 160 160 160 160 0 140 0 100 0 70 ns ns ns ns ns ns ns ns ns ns ns Note
tOW
5
5
5
5
5
5
ns
Note The output load is 1TTL + 5 pF. Remark These AC characteristics are in common regardless of package types.
12
Data Sheet M14274EJ3V0DS00
PD442012L-X
Write Cycle Timing Chart 1 (/WE Controlled)
tWC Address (Input) tCW1 /CE1 (Input) tCW2 CE2 (Input) tAW tAS /WE (Input) tWP tWR
tBW /LB, /UB (Input) tOW tWHZ I/O (Input / Output) Indefinite data out High impedance tDW Data in tDH High impedance Indefinite data out
Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated. 2. When I/O pins are in the output state, do not apply to the I/O pins signals that are opposite in phase with output signals. Remarks 1. Write operation is done during the overlap time of a low level /CE1, /WE, /LB and/or /UB, and a high level CE2. 2. If /CE1 changes to low level at the same time or after the change of /WE to low level, or if CE2 changes to high level at the same time or after the change of /WE to low level, the I/O pins will remain high impedance state. 3. When /WE is at low level, the I/O pins are always high impedance. When /WE is at high level, read operation is executed. Therefore /OE should be at high level to make the I/O pins high impedance.
Data Sheet M14274EJ3V0DS00
13
PD442012L-X
Write Cycle Timing Chart 2 (/CE1 Controlled)
tWC Address (Input)
tAS /CE1 (Input) tCW2 CE2 (Input) tAW tWP /WE (Input)
tCW1
tWR
tBW /LB, /UB (Input) tDW High impedance I/O (Input) Data in tDH High impedance
Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated. 2. When I/O pins are in the output state, do not apply to the I/O pins signals that are opposite in phase with output signals. Remark Write operation is done during the overlap time of a low level /CE1, /WE, /LB and/or /UB, and a high level CE2.
14
Data Sheet M14274EJ3V0DS00
PD442012L-X
Write Cycle Timing Chart 3 (CE2 Controlled)
tWC Address (Input)
tCW1 /CE1 (Input)
tAS CE2 (Input) tAW tWP /WE (Input)
tCW2
tWR
tBW /LB, /UB (Input) tDW High impedance I/O (Input) Data in tDH High impedance
Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated. 2. When I/O pins are in the output state, do not apply to the I/O pins signals that are opposite in phase with output signals. Remark Write operation is done during the overlap time of a low level /CE1, /WE, /LB and/or /UB, and a high level CE2.
Data Sheet M14274EJ3V0DS00
15
PD442012L-X
Write Cycle Timing Chart 4 (/LB, /UB Controlled)
tWC Address (Input)
tCW1 /CE1 (Input) tCW2 CE2 (Input) tAW tWP /WE (Input) tWR
tAS /LB, /UB (Input)
tBW
tDW High impedance I/O (Input) Data in
tDH High impedance
Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated. 2. When I/O pins are in the output state, do not apply to the I/O pins signals that are opposite in phase with output signals. Remark Write operation is done during the overlap time of a low level /CE1, /WE, /LB and/or /UB, and a high level CE2.
16
Data Sheet M14274EJ3V0DS00
PD442012L-X
Low VCC Data Retention Characteristics (TA = -25 to +85 C)
Parameter Symbol Test Condition VCC 2.7 V VCC 2.2 V VCC 1.8 V Unit
PD442012L -BxxX
PD442012L -CxxX
PD442012L -DxxX
MIN. TYP. MAX. MIN. TYP. MAX. MIN. TYP. MAX. Data retention supply voltage VCCDR1 /CE1 VCC - 0.2 V, CE2 VCC - 0.2 V CE2 0.2 V /LB = /UB VCC - 0.2 V, /CE1 0.2 V, CE2 VCC - 0.2 V VCC = 3.0 V, /CE1 VCC - 0.2 V, CE2 VCC - 0.2 V or CE2 0.2 V VCC = 3.0 V, CE2 0.2 V VCC = 3.0 V, /LB = /UB VCC - 0.2 V, /CE1 0.2 V, CE2 VCC - 0.2 V 0 2.0 3.6 1.5 3.6 1.5 3.6 V
VCCDR2 VCCDR3
2.0 2.0
3.6 3.6
1.5 1.5
3.6 3.6
1.5 1.5
3.6 3.6
Data retention supply current
ICCDR1
0.3 0.3 0.3
4 4 4
0.3 0.3 0.3
4 4 4
0.3 0.3 0.3
4 4 4
A
ICCDR2 ICCDR3
Chip deselection to data retention mode Operation recovery time
tCDR
0
0
ns
tR
tRCNote
tRCNote
tRCNote
ns
Note tRC : Read cycle time
Data Sheet M14274EJ3V0DS00
17
PD442012L-X
Data Retention Timing Chart
(1) /CE1 Controlled
tCDR 3.0 V VCC (MIN.)
Note
Data retention mode
tR
VCC
/CE1 VIH (MIN.) VCCDR (MIN.) /CE1 VCC - 0.2 V
VIL (MAX.)
GND
Note B version : 2.7 V, C version : 2.2 V, D version : 1.8 V Remark On the data retention mode by controlling /CE1, the input level of CE2 must be VCC - 0.2 V or 0.2 V. The other pins (Address, I/O, /WE, /OE, /LB, /UB) can be in high impedance state. (2) CE2 Controlled
tCDR 3.0 V VCC (MIN.)
Note
Data retention mode
tR
VCC
VIH (MIN.) VCCDR (MIN.) CE2
VIL (MAX.) CE2 0.2 V GND
Note B version : 2.7 V, C version : 2.2 V, D version : 1.8 V Remark The other pins (/CE1, Address, I/O, /WE, /OE, /LB, /UB) can be in high impedance state.
18
Data Sheet M14274EJ3V0DS00
PD442012L-X
(3) /LB, /UB Controlled
tCDR 3.0 V VCC (MIN.)
Note
Data retention mode
tR
VCC
/LB, /UB VIH (MIN.) VCCDR (MIN.) /LB, /UB VCC - 0.2 V
VIL (MAX.)
GND
Note B version : 2.7 V, C version : 2.2 V, D version : 1.8 V Remark On the data retention mode by controlling /LB and /UB, the input level of /CE1 and CE2 must be VCC - 0.2 V or 0.2 V. The other pins (Address, I/O, /WE, /OE) can be in high impedance state.
Data Sheet M14274EJ3V0DS00
19
PD442012L-X
Package Drawings
5
48-PIN PLASTIC TSOP(I) (12x18)
1 48 F G R detail of lead end
Q 24 25 E P I J A
L S
S D K N S
C MM
B
NOTES 1. Each lead centerline is located within 0.10 mm of its true position (T.P.) at maximum material condition. 2. "A" excludes mold flash. (Includes mold flash : 12.4 mm MAX.)
ITEM A B C D E F G I J K L M N P Q R S
MILLIMETERS 12.00.1 0.45 MAX. 0.5 (T.P.) 0.220.05 0.10.05 1.2 MAX. 1.00.05 16.40.1 0.80.2 0.1450.05 0.5 0.10 0.10 18.00.2 +5 3 -3 0.25 0.600.15 S48GY-50-MJH1-1
20
Data Sheet M14274EJ3V0DS00
PD442012L-X
5
48-PIN PLASTIC TSOP(I) (12x18)
detail of lead end 1 48 E S Q L
R G F
24
25
K
N
S S
D C
MM B
I P
J
A
NOTES 1. Each lead centerline is located within 0.10 mm of its true position (T.P.) at maximum material condition. 2. "A" excludes mold flash. (Includes mold flash : 12.4 mm MAX.)
ITEM A B C D E F G I J K L M N P Q R S
MILLIMETERS 12.00.1 0.45 MAX. 0.5 (T.P.) 0.220.05 0.10.05 1.2 MAX. 1.00.05 16.40.1 0.80.2 0.1450.05 0.5 0.10 0.10 18.00.2 3 +5 -3 0.25 0.600.15 S48GY-50-MKH1-1
Data Sheet M14274EJ3V0DS00
21
PD442012L-X
Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the PD442012L-X.
Types of Surface Mount Device
PD442012LGY-BxxX-MJH: 48-pin Plastic TSOP (I) (12x18) (Normal bent) PD442012LGY-BxxX-MKH: 48-pin Plastic TSOP (I) (12x18) (Reverse bent) PD442012LGY-CxxX-MJH: 48-pin Plastic TSOP (I) (12x18) (Normal bent) PD442012LGY-CxxX-MKH: 48-pin Plastic TSOP (I) (12x18) (Reverse bent) PD442012LGY-DxxX-MJH: 48-pin Plastic TSOP (I) (12x18) (Normal bent) PD442012LGY-DxxX-MKH: 48-pin Plastic TSOP (I) (12x18) (Reverse bent)
22
Data Sheet M14274EJ3V0DS00
PD442012L-X
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
Data Sheet M14274EJ3V0DS00
23
PD442012L-X
* The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. * NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. * Descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. * While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. * NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance.
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